Use assert to automatically verify results rather than visually checking waveforms.
-- GOOD: Default assignment prevents latches process(sel_i, data_a_i, data_b_i) begin data_o <= (others => '0'); -- Default assignment if sel_i = '1' then data_o <= data_a_i; else data_o <= data_b_i; end if; end process; Use code with caution. 4. Clocking, Resets, and Timing Closure effective coding with vhdl principles and best practice pdf
: A critical part of the book distinguishes between VHDL code meant for simulation (testbenches) and code meant to be synthesized into actual hardware. It explains the key characteristics of synthesizable code, helping designers avoid common pitfalls where simulation works perfectly but the synthesized hardware does not. Use assert to automatically verify results rather than