Output delay specifies the time required by an external device downstream to successfully capture data leaving the chip.
# Create a 500 MHz clock with a 50% duty cycle on port 'clk' create_clock -name sys_clk -period 2.0 [get_ports clk] Use code with caution. Generated Clocks
| | Example SDC Command | Description | | :--- | :--- | :--- | | Basic Clock | create_clock -period 5.0 [get_ports CLK] | Creates a clock on port CLK with a period of 5.0 ns and default 50% duty cycle. | | Generated Clock | create_generated_clock -source [get_ports CLK] -divide_by 2 [get_pins U1/Q] | Creates a clock at pin U1/Q that is half the frequency of the master clock at CLK . | | Virtual Clock | create_clock -period 10.0 -name VIRT_CLK | Defines an ideal clock VIRT_CLK to be used for I/O constraints. |
Output delay specifies the time required by an external device downstream to successfully capture data leaving the chip.
# Create a 500 MHz clock with a 50% duty cycle on port 'clk' create_clock -name sys_clk -period 2.0 [get_ports clk] Use code with caution. Generated Clocks synopsys timing constraints and optimization user guide 2021
| | Example SDC Command | Description | | :--- | :--- | :--- | | Basic Clock | create_clock -period 5.0 [get_ports CLK] | Creates a clock on port CLK with a period of 5.0 ns and default 50% duty cycle. | | Generated Clock | create_generated_clock -source [get_ports CLK] -divide_by 2 [get_pins U1/Q] | Creates a clock at pin U1/Q that is half the frequency of the master clock at CLK . | | Virtual Clock | create_clock -period 10.0 -name VIRT_CLK | Defines an ideal clock VIRT_CLK to be used for I/O constraints. | Output delay specifies the time required by an